RESULT_FORMAT=0, RST_B=0, MSTR_EN=0, LPM_EN=0
Control Register
STRTUP_CNT | Start up count |
RESULT_FORMAT | Result Format 0 (0): Left justified 2’s complement 32-bit : SVVVVVVVVVVVVVVVVVVVVVVV00000000 where (S= sign bit , V=valid result value, 0=zero) 1 (1): Right justified 2’s complement 32-bit : SSSSSSSSSVVVVVVVVVVVVVVVVVVVVVVV where (S= sign bit , V= valid result value, 0= zero) |
DLY_OK | Delay OK |
RST_B | Software Reset 0 (0): All ADCs, PGAs and Decimation filters are disabled. Clock Configuration bits will be reset. 1 (1): .= All ADCs, PGAs and Decimation filters are enabled. |
LPM_EN | Low power Mode enable 0 (0): AFE will be in normal mode 1 (1): AFE will be in low power mode. Setting this bit reduce the current consumption of ADC and Buffer Amplifier , the max modulator clock frequency is below 1Mhz. |
SOFT_TRG3 | Software Trigger3 |
SOFT_TRG2 | Software Trigger2 |
SOFT_TRG1 | Software Trigger1 |
SOFT_TRG0 | Software Trigger0 |
MSTR_EN | AFE Master Enable 0 (0): All ADCs are disabled. 1 (1): All ADCs and filters will get simultaneously enabled . |